LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY adder_32bit_broken IS
   PORT(
		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
       );
END adder_32bit_broken;

ARCHITECTURE structure OF adder_32bit_broken IS

COMPONENT adder_32bit IS
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
END COMPONENT;

SIGNAL adder_result	:	STD_LOGIC_VECTOR(31 DOWNTO 0);

BEGIN

result(31 downto 1) <= adder_result(31 downto 1);
result(0) <= '1';

adder: adder_32bit port map(dataa,datab,adder_result);

END structure;       
